1. Field of the Invention
The present invention relates to thin film transistors. More particularly, it relates to thin film transistors that are particularly useful as switching devices in liquid crystal displays, and to methods of fabricating such thin film transistors.
2. Discussion of the Related Art
Active layers of thin film transistors (hereinafter abbreviated TFTs) are formed on substrates. Such active layers include source and drain regions comprised of impurity doped materials and an undoped channel region. Impurity doping means that impurities are implanted into a substrate layer.
Impurities in source and drain regions tend to gather near the channel region when an ON signal is applied to a gate electrode located adjacent the active layer, thereby providing a path through which carriers can more easily pass.
To dope a semiconductor layer, doping impurities are accelerated using an acceleration voltage to kinetic energies in the range of 1 kV to 10 MV. The accelerated impurities are then directed onto a surface of a semiconductor. The accelerated impurities contact crystal lattices of the semiconductor and transfer their kinetic energy to those lattices. The doping impurities achieve an average penetration depth into the semiconductor that is referred to as the projected range (hereinafter abbreviated Rp).
While the projection range is a useful measure of the average penetration depth of the impurities, not every impurity locates at the projection range. Referring now to FIG. 1, doping impurities typically distribute with an impurity concentration profile that is almost symmetrically centering around the projected range Rp. The impurity concentration profile generally follows a Gaussian distribution having a maximum impurity concentration at Rp. FIG. 1 also illustrates a measure of a distributional deviation called ΔRp.
FIG. 2 and FIG. 3 present various illustrations of a related art TFT. FIG. 2 illustrates a cross-sectional view of that related art TFT, while FIG. 3 presents a graph of doping impurity concentration versus depth (into a semiconductor layer) of that related art TFT. Referring now to FIG. 2, a semiconductor layer 21 is formed on a buffer layer 20 that is over a substrate 200. Over the center of the semiconductor layer is a gate insulating layer 22 that is covered by a gate electrode 23. At one side of the semiconductor layer 21 is a source region 21S that is doped with impurities, while the other side of the semiconductor layer has a drain region 21D that is also doped with impurities. Below the gate insulating layer 22 is an undoped channel region 21C.
To fabricate the related art TFT illustrated in FIGS. 2 and 3, impurity doping is carried out by accelerating doping impurities such that Rp is located less than 100 Å from the surface of the semiconductor layer 21. Thus, the source and drain regions 21S and 21D are formed, as shown FIG. 3, by heavily doping the surface of the semiconductor layer 21 with impurities.
Unfortunately, TFTs according to FIGS. 2 and 3 tend to have high leakage currents due to the high doping impurity concentrations at or near the surface of the semiconductor layer when the TFT is in the OFF state. This leakage current is produced by current flow generated by carriers in the drain region when an electric field exists between the drain and gate electrode when the TFT is OFF. One approach to the problem of high leakage current is to incorporate an offset region between the gate and drain to reduce the electric field, the so-called lightly-doped-drain (LDD) structure. However, lightly-doped-drain TFTs usually require relatively complicated fabrication processes that include additional photo-masking and impurity doping steps to form the offset regions.
Moreover, TFTs according to FIGS. 2 and 3 also have relatively high leakage current because of contaminants that cross the interface between the semiconductor layer and the buffer layer during the fabrication of the TFT.
Therefore, an improved thin film transistor, and a method of fabricating such a thin film transistor, having decreased leakage current would be beneficial.